1. FIELD OF THE INVENTION
This invention relates to improvements in electronic circuits, and more particularly to improvements in electronic driver circuits of the type used for driving low impedance loads with high currents at fast slew rates.
2. DESCRIPTION OF THE PRIOR ART
In the past, circuits for providing driving voltages, for example, to low impedance loads, have been proposed. One such low impedance load application, for instance, is a multi-phase dc motor in which drive voltages are switchably applied in accordance with a commutation sequence of the stator coils of the motor. It is important in such applications to provide a driving voltage which increases to the required operating voltage as rapidly as possible in response to the input turn-on signal. (The rate at which the output voltage of the driver changes for a step-signal input is referred to herein as the "slew rate" of the driver.) The problem is exacerbated when, in addition to the normal drive voltage switching requirements, power saving techniques such as PWM techniques are employed in which the drive circuits are rapidly switched on and off during peak operating conditions in addition to their normal commutation switching. This has also been a particular problem in other applications, for example, in which the voltage across a capacitive load is required to swing in a very short time. In such applications, fast output rise and fall times are required in order to enable the proper high speed operation envisioned. However, driver circuits used in the past have not been totally successful in providing such fast slew rate requirements.
For example, a typical prior art driver circuit 10 is shown in FIG. 1. The circuit 10 includes a high gain NPN output transistor 11 and a single p-channel FET 12 pre-driver. The NPN transistor 11 has its collector connected to a supply voltage on line 15, and its emitter connected to an output node 16, which is connected in operation to the desired load. The pre-driver p-channel FET 12 has its source connected to the supply voltage on line 15, and its drain connected to the base of the NPN transistor 11. The input to the circuit 10 is applied to the gate of the p-channel FET 12 from input node 17. Usually the input signal has a step function waveform having a very rapid commutation, or falling edge time. Ideally, the waveform of the output signal delivered to the load also has a rapid rise time, tracking the input waveform; however, the capacitive elements in the circuit, notably the capacitance of the base electrode of the NPN transistor 11, need to be charged before the NPN transistor 11 can be turned on. The single p-channel FET 12, on the other hand, can only supply a fixed amount of drive current to charge the base of the transistor 11, thereby defining the rate at which the transistor 11 can be turned on, or switched into conduction.
One solution to address this problem has been to cascade additional bipolar transistors in Darlington-like configurations to achieve a higher current gain to thereby provide higher drive current to the output transistor. The problem with such solutions is that the voltage drop across the driver transistor is increased for each additional stage which is added.